Selective Si3N4 Etching for 3D NAND Manufacturing
Prof. Sangwoo Lim
Department of Chemical and Biomolecular Engineering, Yonsei University, South Korea
Selective Si3N4 etching is one of the most important and challenging processes in the 3D NAND manufacturing. Etch rate of Si3N4 and etch selectivity to SiO2 need to be increased as the number of Si3N4/SiO2 layer increases in 3D NAND devices. In addition, oxide regrowth issue becomes critical as the number of stack layer increases. In this tutorial, the mechanism to improve Si3N4 etching selectivity and strategy to solve oxide regrowth issues in 3D NAND flash memory devices manufacturing are provided.
Prof. Lim received his Ph.D. in Chemical System Engineering from the University of Tokyo. He was a postdoctoral research associate at the Department of Electrical Engineering and Department of Chemistry at Stanford University. He was a Principal Scientist at Motorola (later Freescale Semiconductor). He has been a professor at Yonsei University (Seoul, Korea) since 2005. Currently Prof. Lim is a Lead Organizer of the International Symposium on Semiconductor Cleaning Science and Technology.
Basic principles of cleaning
Dr. Paul W. Mertens, senior member of technical staff Imec, Leuven Belgium.
Abstract
This course provides basic in-sight in contaminants: their impact as well as their interaction with surfaces and fluids and the basic mechanisms of their removal from surfaces. Guidelines are provided to design a cleaning mixture for a specific application.
This course is suited for people who are new in the field or for senior staff who want to refresh their basic understanding of cleaning. The target background level: Master degree in science or applied sciences.
Biography
Paul W. Mertens holds a MSc and a PhD degree in applied sciences (micro-electronics) from the KULeuven and joined IMEC in 1984. Since 1991 his main field of research is Ultra-clean processing, focusing on silicon wafer surface quality and defects, thin gate dielectrics, the effect of and metrology for contamination, as well as cleaning and surface preparation processes. From 2000 till 2014 he was leading the research team and the industrial affiliation program on Ultra Clean processing. Paul Mertens has (co-)authored more than 500 technical and scientific publications and conference contributions including several invited presentations. He has been giving guest lectures on cleaning at different symposia and at different universities. He is (co-)inventor of more than 20 patents. He is also a co-organiser of the Electrochemical Society SCST symposium and the lead organizer of the bi-annual conference ‘Ultra Clean Processing on Semiconductor Surfaces’ (UCPSS). Currently, as a senior member of technical staff he has the role of expert in the area of contamination control, cleaning and surface preparation and introduction of new materials.
Prevention of Contamination from Silicon Wafer Surfaces:”Ultra Clean Technology”
This tutorial provides a basic understanding of contamination, such as particles, metallic contaminants, and surface-absorbed inorganics/organics, and their impact on semiconductor manufacturing yield, and then introduces “ultra-clean wafer surface processing technology with prevention of contamination on wafer surfaces”.
Biography
Dr. Takeshi Hattori is currently Representative Director of Hattori Consulting International and an international technology journalist after 36 years as a distinguished semiconductor research scientist at Sony Corporation in Japan. In the 1970s, he was a visiting researcher and graduate student at Stanford University IC Labs, U.S.A., on a leave of absence from Sony. He is a Fellow/Emeritus of the Electrochemical Society (ECS) and a program committee member of both the UCPSS and ECS SCST symposia.
Gas phase selective isotropic etching of semiconductor materials with and without plasma
Dr. Thorsten B. Lill, Founder of Clarycon nanotechnology research inc., Kalaheo HI USA
Abstract
Two-dimensional scaling of integrated circuits has long driven Moore’s Law. However, as feature sizes approach their physical limits, alternative strategies are required. Monolithic 3D integration has emerged as a promising solution. In addition to the reactive ion etching of deep holes and trenches with high aspect ratios, isotropic and selective etching is essential for populating the resulting scaffolds with laterally integrated devices. While wet etching is commonly employed during early development stages, dry processing techniques—such as thermal atomic layer etching (ALE)—have recently attracted significant interest.
This tutorial explores the fundamentals of thermal etching, including thermal ALE. These plasma-free techniques are compared and contrasted with conventional plasma-based radical etching.
Biography
Thorsten Lill published an influential review on low temperature gas phase etching. He has co-authored over 110 peer-reviewed articles and holds an impressive portfolio of 98 patents. In 2023, he founded Clarycon Nanotechnology Research, leveraging his extensive 30 years of experience in semiconductor processing.